From 8491a9c6516d76ac6ce920d53c443999c9d82d98 Mon Sep 17 00:00:00 2001
From: "Lukas F. Hartmann" <lukas@mntre.com>
Date: Wed, 7 Sep 2022 06:22:49 +0200
Subject: [PATCH 2/9] pci-imx6-add-support-for-internal-refclk-imx8mq

---
 drivers/pci/controller/dwc/pci-imx6.c | 44 +++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
index 8956a4678..8d443acf2 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
@@ -192,6 +192,31 @@ mipi_dsi_out: endpoint {
 	};
 };
 
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio5 7 GPIO_ACTIVE_LOW>;
+	internal-refclk;
+
+	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+		<&clk IMX8MQ_CLK_PCIE1_AUX>,
+		<&clk IMX8MQ_CLK_PCIE1_PHY>,
+		<&clk IMX8MQ_CLK_MON_CLK2_OUT>;
+
+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+
+	assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
+		<&clk IMX8MQ_CLK_PCIE1_PHY>,
+		<&clk IMX8MQ_CLK_MON_CLK2_OUT>;
+	assigned-clock-rates = <250000000>,
+		<100000000>,
+		<100000000>;
+	assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+		<&clk IMX8MQ_SYS2_PLL_100M>;
+
+	status = "okay";
+};
+
 &pcie1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie1>;
@@ -310,6 +335,12 @@ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
 		>;
 	};
 
+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7		0x16
+		>;
+	};
+
 	pinctrl_pcie1: pcie1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 7a285fb0f..7257e78c7 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -67,6 +67,7 @@ struct imx6_pcie {
 	struct dw_pcie		*pci;
 	int			reset_gpio;
 	bool			gpio_active_high;
+	bool			internal_refclk;
 	bool			link_is_up;
 	struct clk		*pcie_bus;
 	struct clk		*pcie_phy;
@@ -617,6 +618,40 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 	}
 }
 
+#define IMX8MQ_ANA_PLLOUT_REG			0x74
+#define IMX8MQ_ANA_PLLOUT_CKE			BIT(4)
+#define IMX8MQ_ANA_PLLOUT_SEL_MASK		0xF
+#define IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1		0xB
+#define IMX8MQ_ANA_PLLOUT_DIV_REG		0x7C
+#define IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV		0x7
+
+static void imx6_pcie_enable_internal_refclk(void)
+{
+	uint32_t val;
+	struct device_node* np;
+	void __iomem *base;
+
+	np = of_find_compatible_node(NULL, NULL,
+				"fsl,imx8mq-anatop");
+	base = of_iomap(np, 0);
+	WARN_ON(!base);
+
+	val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+	val &= ~IMX8MQ_ANA_PLLOUT_SEL_MASK;
+	val |= IMX8MQ_ANA_PLLOUT_SEL_SYSPLL1;
+	writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+	/* SYS_PLL1 is 800M, PCIE REF CLK is 100M */
+	val = readl(base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+	val |= IMX8MQ_ANA_PLLOUT_SYSPLL1_DIV;
+	writel(val, base + IMX8MQ_ANA_PLLOUT_DIV_REG);
+
+	val = readl(base + IMX8MQ_ANA_PLLOUT_REG);
+	val |= IMX8MQ_ANA_PLLOUT_CKE;
+	writel(val, base + IMX8MQ_ANA_PLLOUT_REG);
+
+	usleep_range(9000,10000);
+}
+
 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 {
 	unsigned int mask, val;
@@ -637,6 +672,9 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 
 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
+	if (imx6_pcie->internal_refclk)
+		imx6_pcie_enable_internal_refclk();
+
 	switch (imx6_pcie->drvdata->variant) {
 	case IMX8MM:
 		/*
@@ -652,7 +690,8 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 		regmap_update_bits(imx6_pcie->iomuxc_gpr,
 				   imx6_pcie_grp_offset(imx6_pcie),
 				   IMX8MQ_GPR_PCIE_REF_USE_PAD,
-				   IMX8MQ_GPR_PCIE_REF_USE_PAD);
+				   (imx6_pcie->internal_refclk ?
+						0 : IMX8MQ_GPR_PCIE_REF_USE_PAD));
 		/*
 		 * Regarding the datasheet, the PCIE_VPH is suggested
 		 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
@@ -1102,7 +1141,8 @@ static int imx6_pcie_probe(struct platform_device *pdev)
 		imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
 		if (IS_ERR(imx6_pcie->pcie_aux))
 			return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
-					     "pcie_aux clock source missing or invalid\n");
+							 "pcie_aux clock source missing or invalid\n");
+		imx6_pcie->internal_refclk = of_property_read_bool(node, "internal-refclk");
 		fallthrough;
 	case IMX7D:
 		if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
-- 
2.36.1

